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71M6511/71M6511H
Single-Phase Energy Meter IC
A Maxim Integrated Products Brand
DATA SHEET
NOVEMBER 2010
SSI Signal
LCD Segment
Output Pin
SCLK
SSDATA
SFR
SRDY
SEG3
SEG4
SEG5
SEG6
Table 59: SSI Pin Assignment
SRDY is an optional handshake input that indicates that the DSP or data-logging device is ready to receive data. SRDY must
be high to enable SFR to rise and initiate the transfer of the next field. It is expected that SRDY changes state on the rising
edges of SCLK. If SRDY is not high when the SSI port is ready to transmit the next field, transmission will be delayed until it is.
SRDY is ignored except at the beginning of a field transmission. If SRDY is not enabled (by SSI_RDYEN ), the SSI port will
behave as if SRDY is always one.
SSDATA is the serial output data. SSDATA changes on the rising edge of SCLK and outputs the contents of a block of CE
RAM words starting with address SSI_STRT and ending with SSI_END . The words are output MSB first.
The field size is set with the SSI_FSIZE register: 0 entire data block, 1-8 bit fields, 2-16 bit fields, 3-32 bit fields. The polarity of
the SFR pulse can be inverted with SSI_FPOL . If SRDY does not delay it, the first SFR pulse in a frame will rise on the third
SCLK after MUX_SYNC (fourth SCLK if 10MHz). MUX_SYNC can be used to synchronize the fields arriving at the data logger
or DSP.
Page: 46 of 98
? 2005–2010 Teridian Semiconductor Corporation
V2.7
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